Digital System Design with VHDL

At the end of this course, the students should be able to: 1. describe finite state machine and its applications in designing digital circuits; 2. build advanced digital logic circuits by applying various reduction techniques and schemes; 3. operate, debug, simulate and analyse complex digital designs in modern VHDL software; 4. analyse and synthesise digital circuits using commercially available VHDL software; 5. create FPGA designs and implement state-of-the-art ASIC/FPGA design methodologies for computer-aided design of logic circuits; and 6. demonstrate practical skills in designing, synthesising and simulating digital systems.

Finite state machine: definition, Mealy and Moore models, state diagram, state table, transition table. Sequential circuits design using flip-flops; asynchronous, and synchronous circuit design. Algorithm State Machine. Design examples and exercises. Structured design: design constructs, design levels, geometry-based interchange formats, computer aided electronic system design tools, Sshematic circuit capture, hardware description languages, design process (simulation, synthesis), structural design decomposition. Introduction to VHDL: VHDL language abstractions, design hierarchies, VHDL component, lexical description, VHDL source file, data types, data objects, language statements, concurrent VHDL, sequential VHDL, advanced features of VHDL (library, package and subprograms). Structural level modelling, register-transfer level modelling, FSM with data path level modelling, algorithmic level modelling. Introduction of ASIC, types of ASIC, ASIC design process, standard cell ASIC synthesis, FPGA design paradigm, FPGA synthesis, FPGA/CPLD architectures. VHDL design: top-down design flow, verification, simulation alternatives, simulation speed, formal verification, recommendations for verification, writing RTL VHDL code for synthesis, top-down design with FPGA. VHDL synthesis, optimization and mapping, constraints, technology library, delay calculation, synthesis tool, synthesis directives. Computer-aided design of logic circuits.