Digital System Design with VHDL

On completion of this course, the students will be able to: 1. explain VHDL as a programming language; 2. design the combinational and sequential logic circuits using VHDL; 3. design programmable logic devices (PLDs) and networks of arithmetic operations; 4. gain proficiency with VHDL software package and utilise software package to solve problems on a wide range of digital logic circuits.

Finite state machine: definition, mealy and Moore models, state diagram, state table, transition table; sequential circuits design using flip-flops, asynchronous and synchronous circuit design; algorithm state machine; design examples and exercises; structured design: design constructs, design levels, geometry-based interchange formats, computer-aided electronic system design tools, schematic circuit capture, hardware description languages, design process (simulation, synthesis), structural design decomposition; introduction to VHDL: VHDL language abstractions, design hierarchies, VHDL component, lexical description, VHDL source file, data types, data objects, language statements, concurrent VHDL, sequential VHDL, advanced features of VHDL (library, package and sub- programmes); structural level modelling, register-transfer level modelling, FSM with data path level modelling, algorithmic level modelling; introduction of ASIC, types of ASIC, ASIC design process, standard cell ASIC synthesis, FPGA design paradigm, FPGA synthesis, FPGA/CPLD architectures; VHDL Design: top-down design flow, verification, simulation alternatives, simulation speed, formal verification, recommendations for verification, writing RTL VHDL code for synthesis, top-down design with FPGA; VHDL synthesis, optimisation and mapping, constraints, technology library, delay calculation, synthesis tool, synthesis directives; and computer-aided design of logic circuits.